(a) Field of the Invention
The present invention relates to a thin film transistor array panel.
(b) Description of Related Art
Generally, a liquid crystal display (LCD) includes a liquid crystal (LC) panel unit including two panels provided with pixel electrodes and a common electrode, and an LC layer with dielectric anisotropy interposed therebetween.
The pixel electrodes are arranged in a matrix and are connected to switching elements such as thin film transistors (TFTs) to be sequentially applied with a data voltage for each row. The common electrode covers the entire surface of the upper panel and is supplied with a common voltage. A pixel electrode, the common electrode, and the LC layer form an LC capacitor in a circuit, and the LC capacitor together with a switching element connected thereto is a basic unit of a pixel.
The LCD displays images by applying an electric field to the LC layer disposed between the two panels and regulating the strength of the electric field to adjust transmittance of light passing through the LC layer.
The LCD, which is used as a small and medium sized display device such as a portable telephone, includes a display panel assembly, a driving flexible printed circuit (FPC) provided with signal lines to transmit input signals from external devices, and an integration chip that controls the above-described elements.
The LCD includes a panel unit provided with pixels including switching elements and signal lines for displaying images, a gate driver providing a gate-on voltage and a gate-off voltage for gate lines of the display signal lines to turn on/off the switching elements, and a data driver providing a data signal for data lines of the display signal lines to apply a data voltage to the pixels via the turned-on switching elements. The integration chip generates control signals and driving signals for controlling the panel unit and is generally mounted as a COG (chip on glass).
Also, pad portions, in which a plurality of pads are formed in a predetermined number, are arranged on the edges of the integration chip. The pads are electrically connected to the signal lines of the panel for receiving the signal applied to the inner portion of the panel or the integration chip, and the FPC is connected to the pad portion as a FOG (film on glass). In the manufacturing process, the plurality of pads are commonly electrically connected with a common connecting member for preventing the elements such as the thin film transistors from being damaged by electrostatic energy generated in the manufacturing process, and the common connection member is separated from the plurality of pads for electrically insulating the plurality of pads from each other.
However, conductive particles may remain due to steps of the insulating layer formed in the panel in the portion where the common connection member and the pads are connected to each other in the manufacturing process, such that signal drive level defects may occur.